In the continued evolution of integrated circuit (IC) technology, geometric scaling has reduced components to sizes that have become increasingly challenging to produce. To advance the semiconductor industry to the next level, three-dimensional (3D) packaging has been growing in development since the 1980's. In 3D packaging, chips are stacked vertically on each other, which provides many advantages such as denser circuitry, heterogeneous integration, and faster interconnections due to the shorter distance between layers compared to conventional wirebonds. Connections between layers in 3D IC's are typically achieved through the use of through-silicon vias (TSV's), which are conductive paths through a silicon wafer or die. The ability to produce TSV's of the necessary sizes and accuracy to meet the demands of 3D packaging technology, with cost effective methods, is of key importance to the development of this industry.